(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for filling an insulation layer in a narrow trench of a small device while avoiding the formation of a void.
(b) Description of the Related Art
Shallow trench isolation (STI) is frequently used as an isolation structure in a semiconductor device. In STI, a trench is formed in a semiconductor substrate, and an insulation material is filled in the trench. Since the formation is limited to the size of the trench, which has as its object size a field region size, this configuration works favorably toward making the semiconductor device small.
It is important in STI to completely fill the trench with the insulation material without the formation of voids. U.S. Pat. Nos. 6,544,871, 4,528,047, 4,680,614, 6,180,490, 5,801,083, 6,524,931 are conventional techniques related to STI.
FIG. 1 shows a sectional view of a conventional STI structure. To form the conventional STI structure, a pad oxidation layer 2 is formed on a semiconductor substrate 1 to a thickness of approximately 200 Å. A silicon nitride layer 3 is then deposited on the pad oxidation layer 2, after which a photoresist layer is deposited on the silicon nitride layer 3. Next, the photoresist layer is exposed and developed such that an area thereof corresponding to where a trench is to be formed is removed. This results in the formation of a photoresist pattern (not shown).
Subsequently, using the photoresist pattern as a mask, the exposed portion of the silicon nitride layer 3, then the pad oxidation layer 2 and a predetermined section of the semiconductor substrate 1 (i.e., a section corresponding to a predetermined depth) under the removed section of the pad oxidation layer 2, are dry-etched. A trench 100 is therefore formed in the semiconductor substrate 1. The photoresist pattern is removed after the formation of the trench 100, then a cleaning process is performed.
Subsequently, a liner oxidation layer 4 is formed over all exposed elements of the silicon nitride layer 3 and inner walls of the trench 100, after which a trench oxidation layer 5 is thickly deposited on the liner oxidation layer 4 until at least the trench 100 is completely filled.
The liner oxidation layer 4 minimizes the stress transferred to the trench region during deposition of the trench oxidation layer 5. The liner oxidation layer 4 also prevents the uneven formation of the trench oxidation layer 5 caused by differences in deposition speeds of the semiconductor substrate 1 and the silicon nitride layer 3. That is, the difference in the materials of the semiconductor substrate 1 and the silicon nitride layer 3 is such that their deposition speeds differ. In addition, with the formation of the liner oxidation layer 4, upper corner areas of the semiconductor substrate 1 adjacent to the trench 100 are rounded (i.e., prevented from being sharply pointed) following a subsequent trench isolation process.
Next, chemical-mechanical polishing is performed on the trench oxidation layer 5 and the liner oxidation layer 4 until the silicon nitride layer 3 is exposed, that is, until the trench oxidation layer 5 and the liner oxidation layer 4 are flattened and flush with the silicon nitride layer 3. This completes the trench isolation process.
However, if an aspect ratio of the trench is increased by a reduction in trench width and an increase in trench depth in an attempt to increase the degree of integration of the device, there is a greater possibility of a void 6 being formed in the trench 100. That is, an entrance of the trench 100 may be partially blocked before a deep area thereof is filled during deposition of the trench oxidation layer 5. The formation of a void 6, therefore, prevents the trench 100 from being completely filled.
Using present trench filling techniques, the formation of voids may be avoided with trenches of a width of 0.24 μm or greater. However, any reduction in the width to, for example, 0.21 μm or 0.18 μm results in the formation of voids.
The formation of a void 6 in the trench oxidation layer 5 as described above may result in the void 6 being exposed following chemical-mechanical polishing to flatten the trench oxidation layer 5. If this occurs, polysilicon deposited to form an electrode in a subsequent process enters the void 6 such that leakage current develops. This results in severe malfunctioning of the device.